XCENA's $135M Series B Targets AI Memory Wall via CXL 3.x

South Korean semiconductor startup XCENA secured $135 million in Series B funding at a post-money valuation of $570 million. The round, co-led by Atinum Ventures and IMM Investment, brings the company’s total funding to $185 million. XCENA is building compute-near-memory hardware to address the severe latency and energy bottlenecks caused by moving data between processors and memory modules during AI inference.

As generative AI scales, model execution shifts heavily toward the decode phase, where tokens are generated sequentially. This workload is highly memory-bound. Sourcing high-bandwidth memory (HBM) has become a primary operational constraint, with prices surging 246% in 2025 and major suppliers sold out through 2026.

The MX1 Architecture

XCENA’s flagship prototype, the MX1 chip, functions as a computational memory controller. Instead of relying entirely on external GPUs or CPUs to process data, the MX1 integrates thousands of small RISC-V cores directly adjacent to DDR5 DRAM modules.

The hardware connects directly to the CPU using the Compute Express Link (CXL) 3.x standard. This topology allows the memory unit itself to handle data-heavy tasks like preprocessing, data caching, and KV cache management. By processing data where it resides, the MX1 bypasses the constant round trips over the system bus that typically throttle memory-bound workloads.

The “memory wall” dictates the upper limits of hardware utilization. When a processor must wait for data to traverse the motherboard, compute cycles sit idle. By embedding RISC-V cores next to the DDR5 modules, the MX1 essentially turns passive storage into an active processing node.

XCENA claims this architectural shift reduces data movement overhead enough to consolidate workloads that currently require 10 servers onto a single machine. The MX1 controller supports up to 2TB of memory natively. For larger deployments, a feature called InfiniteMemory expands capacity to the petabyte scale using SSD backends.

Market Positioning

XCENA targets hyperscale cloud providers and large AI infrastructure operators. The company is positioning the MX1 against connectivity solutions from established vendors like Astera Labs and Marvell. Investors backed the specialized RISC-V design as a more efficient alternative to general-purpose connectivity hardware.

The funding round included participation from Corstone Asia, Korea Development Bank (KDB), KDB Capital, Kiwoom Investment, and DSC Investment. Existing backers SBI Investment and Mirae Asset Capital also joined the Series B. This capital injection provides the runway needed to finalize the silicon design and secure foundry capacity.

The startup’s leadership team consists of veterans from Samsung Electronics and SK Hynix, including CEO Jin Kim, CTO Dohun Kim, and CPO Harry Juhyun Kim.

Production Timeline

XCENA will manufacture the MX1 using Samsung’s 4nm foundry process. Production chips are scheduled to roll off the lines by late 2026. The company projects initial revenue generation in 2027.

If you manage large-scale hardware deployments for generative models, evaluate CXL 3.x computational memory architectures as part of your 2027 capacity planning. Shifting compute to the memory controller offers a viable path to scale inference workloads without competing directly for limited HBM supply.