Modular 3nm MTIA v3 Chips Enter Production for Meta Inference

Meta is moving its next-generation custom silicon into mass production, according to a technical briefing detailed this week. The MTIA v3, or Meta Training and Inference Accelerator version 3, marks a shift from monolithic chip design to a modular, disaggregated architecture. This allows the infrastructure team to swap specific networking or memory tiles without redesigning the core compute units.

Tile-Based Architecture and 3nm Process

The new accelerators are manufactured on TSMC’s N3P 3nm-class process. This represents a significant density and efficiency upgrade over the 5nm process used for the MTIA v2 release in early 2024. By separating compute and memory interfaces into distinct silicon tiles, the hardware can adapt more quickly to changing memory-to-compute ratios required by state-space models and Transformer variants.

At the package level, the v3 includes a built-in scaling fabric. This integrated networking layer handles the high-bandwidth demands of distributed AI inference across thousands of nodes. The hardware remains tightly coupled with PyTorch and Meta’s Triton-based compiler stack, allowing developers to target the new silicon with minimal code adjustments.

Throughput Targets and Cost Reductions

Meta engineered the MTIA v3 specifically for its ranking and recommendation algorithms across Facebook and Instagram. While the hardware can serve generative models like Llama 4, the company will continue using NVIDIA GPUs for large-scale pre-training workloads.

The shift to custom 3nm silicon changes the baseline economics of high-volume inference. Analysts estimate the internal production cost of the v3 chips is roughly 40 percent lower than purchasing commercial H-series or B-series processors for equivalent tasks.

Specification	MTIA v2 (Artemis)	MTIA v3
Process Node	5nm	TSMC N3P (3nm)
Architecture	Monolithic	Disaggregated Tiles
Throughput (Rec Models)	Baseline	3.5x
Energy Efficiency	Baseline	2.8x

Deployment Timeline

The initial v3 tiles have completed the tape-out phase. Mass production at TSMC will begin in September 2026. This timeline aligns with the activation of Meta’s upcoming liquid-cooled data centers in the United States and Europe.

The chips are scheduled to hit production data center racks by the end of Q1 2027. If you manage large-scale recommendation systems, Meta’s strategy highlights the growing necessity of purpose-built accelerators to control power and unit costs at scale.