Intel's GPU D-Series Targets Inference: Up to 480GB LPDDR5X on a 350W PCIe Card

Intel’s long-teased Crescent Island AI accelerator has a product name and a spec sheet: the GPU D-series, unveiled in Intel’s OCP Global Summit keynote on October 13 and formalized on product pages since. The headline configuration: 1.3 petaflops of FP8 compute, 1.5 TB/s of memory bandwidth, and up to 480GB of LPDDR5X, built on the Xe3P architecture, in a standard air-cooled PCIe card drawing 350W. The 480GB figure needs a footnote that matters: Intel’s own branded card carries 160GB, and the 480GB configurations come from ODM partners using the flexible memory design. Customer sampling is underway, with OEMs, ODMs, neoclouds, and AI-native companies building validated platforms.

The memory bet, explained

The D-series is deliberately unbalanced by GPU standards: modest compute, enormous memory, standard mechanics. Intel’s positioning is that the binding constraint for production inference is no longer FLOPS but capacity and bandwidth per dollar, because serving means holding weights, KV cache, and concurrent batches in memory while keeping latency flat under load. The numbers back the framing: 300B parameters fit on one card, and an 8-GPU system exceeds a trillion, no liquid cooling or special rack required. That last part is the quiet revolution; a 350W PCIe card drops into existing servers, which means the addressable market is every company with x86 capacity sitting idle, not just new AI data centers. The trade-off is equally explicit: at 1.3 PFLOPS FP8, the D-series is nowhere near Blackwell-class compute, so training and low-latency frontier serving stay on Nvidia. Intel is racing for the workhorse tier, and Intel’s VP of AI products, Anil Nanduri, said the quiet part aloud: “Inference is becoming the defining AI workload.”

Agentic AI as the design target

EVP Kevork Kechichian’s framing is that “agentic AI is changing what customers need from their data centers,” and Intel’s version of that argument is concrete: agents spend their time in multi-step workflows of retrieval, reasoning, orchestration, and tool use, where the same model gets invoked thousands of times under latency targets, and concurrency-per-watt beats peak throughput. Intel proposes measuring inference hardware by concurrent agents sustained at target latency rather than benchmark FLOPS, which is the same reframing this site has tracked all month: DeepSeek shipping search APIs priced per successful request and open labs competing on cost-per-task all push in the direction where memory capacity, not compute, is the scarce input. The rack-level story reinforces it: Intel says select Xeon 6+ configurations exceed 46,000 cores per rack at 133.45 kW for the general-purpose half of agent workloads, with D-series cards handling the model half.

Ecosystem reality check

Hardware is the easy part of Intel’s problem, and the announcement’s software details are the ones that will decide adoption. Intel promises a common Xe software foundation, native upstream integration with standard frameworks and serving engines, and day-zero support for emerging open models, with Meta’s Muse Glimmer cited as an example. That claim will get tested immediately, because the models being served in this tier are exactly the open-weights releases that land weekly, and day-zero on one model means little if the next refresh takes a month of porting. Pricing has not been announced, and at 1.3 PFLOPS FP8 the D-series will live or die on dollars per concurrent agent against Nvidia’s L40S-class parts and the upcoming wave of LPDDR5X inference cards. What to watch: the first ODM cards at 480GB and their actual street pricing, independent serving benchmarks once sampling converts to shipment, and whether the “concurrent agents at target latency” metric Intel is championing gets adopted by the buyers who write checks. If it does, Intel will have changed how inference hardware is bought, which would be worth more than any single spec.